The present invention relates to a system construction of semiconductor devices, that has a plurality of the same semiconductor devices in a cascade connection, and further concerns a liquid crystal display device module using the system construction of the semiconductor devices.
As shown in FIG. 10, a conventional liquid crystal display device module has a semiconductor device system, in which source driver LSI (large Scale Integrated Circuit) chips 51 and gate driver LSI chips 52 are respectively mounted on TCPs (Tape Carrier Package) 53. Further, the output terminals of the source driver LSI chips 51 and the gate driver LSI chips 52 are subjected to a thermocompression bonding and are electrically connected to terminals (not shown) made of ITO (Indium Tin Oxide) on a liquid crystal panel 54 via, for example, an ACF (Anisotropic Conductive Film).
Also, the TCPs 53 are electrically connected with a flexible substrate 55 in the same manner as the output terminals of the source driver LSI chips 51 and the gate driver LSI chips 52. With this arrangement, color image data signals (three kinds of signals, Rxc2x7Gxc2x7B) are supplied to the source driver LSI chips 51, and control signals and source lines, etc. are supplied to the source driver LSI chips 51 or the gate driver LSI chips 52, from a controller circuit 56 via lines disposed on the flexible substrate 55.
Here, eight TCPs 53 have the source driver LSI chips 51 and serve as first through eighth source drivers. Namely, eight source driver LSI chips 51 of the same structure are cascaded. Additionally, in this arrangement, two gate driver LSI chips 52 are cascaded.
In the liquid crystal panel 54, the number of pixels is 800 pixelsxc3x973(RGB)[source]xc3x97600 pixels[gate].
The first through eighth source drivers provide a 64-gray scale display and respectively drive 100 pixelsxc3x973(RGB).
As shown in FIG. 11, each of the source driver LSI chips 51 of the source drivers is constituted by a shift resister circuit 61, a data latch circuit 62, a sampling memory circuit 63, a hold memory circuit 64, a reference source generating circuit 65, a DA converter circuit 66, and an output circuit 67.
In the shift resister circuit 61, as a start pulse, a start-pulse input signal SPI (signal) is outputted from a terminal SSPI of the controller circuit 56 and inputted to a terminal SPin of the source driver LSI chip 51 in synchronization with a horizontal synchronizing signal of the image data signals Rxc2x7Gxc2x7B (signal). Further, afterwards, the shift resister circuit 61 shifts the start-pulse input signal SPI in response to a clock signal CK (reference signal) which is outputted from an SCK terminal of the controller circuit 56.
The start-pulse input signal SPI, which has been shifted in the shift resister circuit 61, is outputted from a terminal SPout of the source driver LSI chip 51 as an output of the final step and inputted to a terminal SPin of the next source driver LSI chip 51. Moreover, the clock signal CK is inputted to an input terminal CKin, outputted from an output terminal CKout, and inputted to a terminal CKin of the next source driver LSI chip 51.
In the same manner, the start pulse input signal SPI is shifted to the final step of the shift resister circuit 61 of the source driver LSI chip 51 in the eighth source driver shown in FIG. 10.
Meanwhile, the image data signals Rxc2x7Gxc2x7B, which are respectively outputted from Rxc2x7Gxc2x7B terminals of the controller circuit 56, are constituted by 6-bit Rxc2x7Gxc2x7B signals. As shown in FIG. 11, the image data signals Rxc2x7Gxc2x7B are respectively inputted in parallel from a terminal R1-6in, a terminal G1-6in, and a terminal B1-6in of the source driver LSI chip 51. And then, the image data signals Rxc2x7Gxc2x7B are temporarily latched in the data latch circuit 62 and are transmitted to the sampling memory circuit 63.
The sampling memory circuit 63 performs a sampling on image signal data containing 6-bit Rxc2x7Gxc2x7B, 18 bits in total, that are transmitted in a time division, in accordance with an output signal from each step of the shift resister circuit 61. The sampling memory circuit 63 stores the sampled image signal data until a latch signal LS (described later), which is outputted from an LS terminal (see FIG. 3, an explanatory drawing of the present invention) of the controller circuit 56, is inputted.
Next, the image signal data is inputted to the hold memory circuit 64, and the latch signal LS latches the image signal data when the image data signals Rxc2x7Gxc2x7B of one horizontal period are inputted to the hold memory circuit 64. And then, the hold memory circuit 64 holds the data until data of the next horizontal period is inputted from the sampling memory circuit 63 to the hold memory circuit 64; meanwhile, the image signal data is outputted.
The reference source generating circuit 65 generates, for example, 64-level voltage for a gray-scale display by using a resistance division, in accordance with a reference voltage which is outputted from a terminal Vref 1-9 (see FIG. 3, an explanatory drawing of the present invention) of the controller circuit 56 and is inputted to a terminal Vref 1-9 of the source driver LSI chip 51.
The DA converter circuit 66 converts digital 6-bit image signals Rxc2x7Gxc2x7B to analog signals. And then, the output circuit 67 amplifies the 64-level analog signals in accordance with a voltage, which is outputted from the controller circuit 56 and is inputted to a terminal VLS of the source driver LSI chip 51, and the analog signals are outputted from output terminals XO1xcx9cXO100, YO1xcx9cYO100, and ZO1xcx9cZO100 to terminals (not shown) of the liquid crystal panel 54.
The output terminals XO, YO, and ZO respectively correspond to the image data signals Rxc2x7Gxc2x7B, and each of XO, YO, and ZO has 100 terminals. Additionally, a terminal Vcc and a terminal GND of the source driver LSI chip 51 are terminals for power supplied to the source driver LSI chip 51. Here, in FIG. 11, a buffer circuit is omitted.
The above description discussed the construction and operation of the source driver having a 64-step gradation.
Here, since the gate driver LSI chip 52 basically has the same construction as the source driver LSI chip 51, the description thereof is omitted.
Regarding such a system construction of the semiconductor devices in the liquid crystal display device module, the number of pixels is increasing and resolution is becoming higher. Due to an increase in the number of pixels, the source driver LSI chips 51 and the gate driver LSI chips 52 need to realize a high-speed transmission of the image data signals Rxc2x7Gxc2x7B, namely, a high-frequency clock operation. This tendency is more outstanding in the source driver LSI chips 51 than in the gate driver LSI chips 52.
For instance, when the source has 800 pixels and the gate has 600 pixels, the clock signal CK is set at nearly 65 MHz.
When the high-frequency clock signal CK is supplied to the each of the source driver LSI chips 51 via the flexible substrate 55, stray capacitance grows so as to deform a clock waveform, resulting in a malfunction. Therefore, in the system construction of the semiconductor devices, as shown in FIG. 10, the adjacent TCPs 53 overlap each other so as to electrically connect wires, and the clock signal CK is outputted via the buffer circuit (not shown) in the source driver LSI chip 51 and is inputted to the next source driver LSI chip 51. This arrangement makes it possible to successively pass the clock signal CK through all the cascaded source driver LSI chips 51 of the first through eighth source drivers.
Japanese Unexamined Patent Publication No. 3684/1994(Tokukaihei 6-3684, published on Jan. 14, 1994) discloses a method in which the adjacent TCPs 53 overlap each other so as to connect wires. In this method, a stray capacitance is small between the source driver LSI chips 51 so as to reduce deformation on a waveform.
However, regarding the conventional system construction of semiconductor devices and the liquid crystal display device module using the system construction of the semiconductor devices, due to a higher frequency of the clock signal CK and a cascade connection of IC chips having the similar properties, the following problem occurs.
Generally, a delay time dt1 resulted from a rise time (when 10% level is raised to 90% level) of the clock signal CK is set so as to be equal to a delay time td2 resulted from a fall time (when 90% level is lowered to 10% level) of the clock signal CK.
For instance, regarding a clock buffer circuit constituted by a P-channel MOS (Metal Oxide Semiconductor) and an N-channel MOS, for example, a gate width of the P-channel MOS is increased to obtain a larger driving ability.
However, the delay time td1 at a rise time cannot be equal to the delay time td2 at a fall time of the clock signal CK. Upon completion of manufacturing, for example, a property difference of nearly 1 nsec. normally appears. Moreover, an LSI threshold voltage Vth varies for each of the LSIs due to a change in processing conditions. Specifically, for example, when the delay time is about 2 nsec. at a rise time, the delay time may be about 3 nsec. at a fall time. FIG. 12 shows a timing chart obtained by cascading the plurality of LSIs and transmitting a signal through the LSIs.
Namely, when N LSI chips having the similar properties are cascaded, a 1 nsec. difference per LSI chip is accumulated to be: the difference in delay time (1 nsec.)xc3x97N. Hence, as shown in FIG. 12, a low-level period is narrowed.
As described above, when the clock signal CK is about 65 MHz, one period is about 15 nsec. and a low-level period is about 8 nsec. at a duty ratio of 50%. Here, upon cascading eight source driver LSI chips 51 (N=8) having the above-mentioned properties, a low-level period of the clock signal CK is less than 1 nsec. in the source driver LSI chip 51 of the final step; therefore, the clock signal CK cannot obtain the minimum tolerance time of the low-level period, that is required for driving the source driver LSI chip 51. Consequently, the source driver LSI chips 51 has a malfunction and lose stability, thereby decreasing reliability.
Furthermore, FIG. 12 shows the input of the clock signal CK to the first source driver on the assumption that the waveform has a duty ratio of 50%. However, in an actual system construction, a stray capacitance becomes the largest on a line from the controller circuit 56 via the wires of the flexible substrate 55 to the first source driver. Additionally, on a line from the controller circuit 56 via the wires of the flexible substrate 55 to the first source driver, the stray capacitance greatly fluctuates due to the construction including the shape of the installed LSI.
The waveform deformation and unevenness affect as well as the accumulation of delay times of the source driver LSI chips 51; thus, it is extremely difficult to grantee reliability until the final step of the source driver LSI chips 51.
Considering a further increase in number of pixels, this problem is serious.
An objective of the present invention is to provide a system construction of semiconductor devices that can prevent a malfunction and a halt of the system so as to construct a highly reliable system when a plurality of the same semiconductor devices are cascaded, and to provide a liquid crystal display device module using the system construction of the semiconductor devices.
In order to achieve the above objective, the system construction of the semiconductor devices of the present invention, in which a plurality of semiconductor devices of similar properties are cascaded, is characterized in that each of the semiconductor devices includes a half-period delaying means which delays a propagation signal and a reference signal by a half period of the reference signal relative to the input signals before outputting the signals, said propagation signal and the reference signal being cascaded and propagated to the plurality of semiconductor devices.
When the plurality of semiconductor devices of similar properties are cascaded, and signals such as a start pulse signal and an image data signal, and a reference signal such as a clock signal are cascaded and propagated to the semiconductor devices, delays appear in each of the semiconductor devices. The delays are supposed to be the same at a rise time and at a fall time of the signals and the reference signal; however, the delay times are different from each other in an actual operation. Consequently, in the semiconductor device located at the end, the accumulation of the delay time differences shortens the low-level periods of the signals and the reference signal so as to cause a malfunction and a halt of the system.
However, according to the present invention, each of the semiconductor devices is provided with the half-period delaying means. The half-period delaying means delays the propagation signals and the reference signal, which are cascaded and propagated to the plurality of cascaded semiconductor devices, by a half period of the reference signal relative to the input signals before outputting the signals.
Namely, the propagation signals and the reference signal are delayed by a half-period of the reference signal relative to the input signals, so that it is possible to shift a rise time and a fall time of the propagation signal and the reference signal between the odd-numbered semiconductor devices and the even-numbered semiconductor devices. Therefore, even when the delay times of the signal and the reference signal are different at a rise time and a fall time in each of the semiconductor devices, the delay times can be cancelled so as to cause no accumulation of the delay time differences. As a result, in the case of the faster reference signal, namely, a faster clock, and an increase in the cascaded semiconductor devices, it is possible to propagate an appropriate clock to the semiconductor device located at the end so as to eliminate the cause of a malfunction.
Hence, upon cascading the plurality of semiconductor devices having a similar property, it is possible to provide the system construction of the semiconductor devices that can prevent a malfunction and a halt of the system so as to construct a highly reliable system.
For a fuller understanding of the nature and advantages of the invention, reference should be made to the ensuing detailed description taken in conjunction with the accompanying drawings.